1. Field of the Invention
The present invention relates to a semiconductor device and a fabricating method thereof, and more particularly to a semiconductor device having a multi-layered wiring including a dummy wiring and a method for fabricating the same.
2. Description of the Related Art
In a semiconductor integrated circuit, with an increase of integration density the wirings become so complicated that formation of a multi-layered wiring is indispensable. An interlayer insulating layer is used to make insulation between a plurality of wiring layers. The interlayer insulating layer also makes insulation between different wiring patterns in a same wiring level.
A silicon oxide layer formed by a chemical vapor deposition (CVD) has an excellent dielectric property. However, it is a conformable or conformal layer having a surface morphology reflecting the surface shape of an underlying layer. When an interlayer insulating layer is formed only by a conformal insulating layer, steps on the surface become large with an increase of a number of the layers of a multi-layered wiring so that such problems as breaking and short-circuiting of the wirings occur.
In order to planarize a surface of the interlayer insulating layer, a method of using an insulating layer having a planarizing property such as a silicon oxide layer formed by spin-on-glass (SOG) or by a tetraethylorthosilicate(TEOS)-ozone is proposed. These insulating layers having a planarizing property eliminate the concaves and convexes on the surface of an underlying layer to a certain extent. However, some problems remain, which include a difficulty of planarizing a wide concave portion to the same extent as a narrow concave portion.
For the wide concave portion, is known a method of using a wiring pattern not contributing to circuit connection of a semiconductor integrated circuit, i.e. a dummy pattern, for eliminating the wide concave portion. For example, there are proposed a method of arranging once temporal wirings in all of the wiring channel regions of a gate array and then cutting off the temporal wirings according to a circuit connection to be realized (for example, refer to JP-A5-275531) and a method of forming dummy patterns in regions where upper level wirings will be formed, but no lower level wiring exists (for example, refer to JP-A 1-239873).
In order to form a dummy wiring pattern, preparation similar to that for forming a usual wiring pattern is necessary. For example, in order to form dummy wiring patterns in all of the vacant regions of a semiconductor chip, quantity of data required for wiring patterns is increased by a factor of 20 to 30. In order to handle such a vast quantity of data, data processing equipment should become large and a long time is required for processing.